1. Field of the Invention
The present invention relates to novel structures of an arithmetic operation unit and a memory device, which utilize two phase states that are acquired by applying a DC bias voltage to single-electron tunneling (SET) junction elements via a series resistor and then applying an AC pump signal thereto to thereby allow the voltage between the junctions of the SET junction elements to be phase-locked to the AC pump signal, and a method of manufacturing the same.
2. Description of the Related Art
Recently have extensive studies been made on a single-electron tunneling effect which permits electrons to tunnel through a thin insulator layer with a small area, placed between two semiconductor layers or metal films, one by one. This invention provides novel structures of an arithmetic operation unit and a memory device, which utilize two stable phase states acquired by implementing phase-locking to an AC pump using the nonlinear characteristics that appear on a single-electron tunneling junction element (hereinafter simply called "SET junction element") that produces such a single-electron tunneling effect.
A phase-locked arithmetic operation circuit and memory circuit which utilize such an SET junction element are disclosed in, for example, the paper written by the present inventor and entitled "Structure of Single-electron Tunneling Phase Logic" in Papers ED96-218 (March 1997) in Institute of Electronic Information Communication Engineering. A device which uses two phase states produced by applying a pump signal of twice the frequency of SET oscillation to an SET junction element has been proposed by Mr. Kiehl in Japanese Patent Application, KOKAI Publication No. 6-48213.
However, most of the conventional reports on SET junction elements simply cover their simulation analysis and operations, and no specific device architectures or no specific fabrication methods therefor have been proposed yet. While theoretically effective operations of phase-locked circuits using SET junction elements have been confirmed and are expected to solve problems of CMOS circuits, currently used widely, on dissipation power and the limited integration scale, which will surely arise in the near future, therefore, there is a strong demand of studying actual structures.